CCNTR_EL0_63to32 (A53_PMU_3) Register Description
Register Name | CCNTR_EL0_63to32 |
---|---|
Offset Address | 0x00000000FC |
Absolute Address | 0x00FEF300FC (CORESIGHT_A53_PMU_3) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Performance Monitors Cycle Counter (high word) |
CCNTR_EL0_63to32 (A53_PMU_3) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CCNT | 31:0 | rwNormal read/write | 0x0 | Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C. |