CEID0_EL0 (A53_PMU_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CEID0_EL0 (A53_PMU_1) Register Description

Register NameCEID0_EL0
Offset Address0x0000000E20
Absolute Address 0x00FED30E20 (CORESIGHT_A53_PMU_1)
Width32
TyperoRead-only
Reset Value0x63FFFFFF
DescriptionPerformance Monitors Common Event Identification Register 0

CEID0_EL0 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CE_31to031:0roRead-only0x63FFFFFFCommon architectural and microarchitectural feature events that can be counted by the PMU event counters.For each bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.BitEvent numberEvent mnemonic310x01FL1D_CACHE_ALLOCATE300x01ECHAIN290x01DBUS_CYCLES280x01CTTBR_WRITE_RETIRED270x01BINST_SPEC260x01AMEMORY_ERROR250x019BUS_ACCESS240x018L2D_CACHE_WB230x017L2D_CACHE_REFILL220x016L2D_CACHE210x015L1D_CACHE_WB200x014L1I_CACHE190x013MEM_ACCESS180x012BR_PRED170x011CPU_CYCLES160x010BR_MIS_PRED150x00FUNALIGNED_LDST_RETIRED140x00EBR_RETURN_RETIRED130x00DBR_IMMED_RETIRED120x00CPC_WRITE_RETIRED110x00BCID_WRITE_RETIRED100x00AEXC_RETURN90x009EXC_TAKEN80x008INST_RETIRED70x007ST_RETIRED60x006LD_RETIRED50x005L1D_TLB_REFILL40x004L1D_CACHE30x003L1D_CACHE_REFILL20x002L1I_TLB_REFILL10x001L1I_CACHE_REFILL00x000SW_INCR