CEID1_EL0 (A53_PMU_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CEID1_EL0 (A53_PMU_0) Register Description

Register NameCEID1_EL0
Offset Address0x0000000E24
Absolute Address 0x00FEC30E24 (CORESIGHT_A53_PMU_0)
Width32
TyperoRead-only
Reset Value0x00000001
DescriptionPerformance Monitors Common Event Identification Register 1

CEID1_EL0 (A53_PMU_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CE_32 0roRead-only0x1Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.BitEvent numberEvent mnemonic00x020L2D_CACHE_ALLOCATE