CEID1_EL0 (A53_PMU_2) Register Description
Register Name | CEID1_EL0 |
---|---|
Offset Address | 0x0000000E24 |
Absolute Address | 0x00FEE30E24 (CORESIGHT_A53_PMU_2) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000001 |
Description | Performance Monitors Common Event Identification Register 1 |
CEID1_EL0 (A53_PMU_2) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CE_32 | 0 | roRead-only | 0x1 | Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.BitEvent numberEvent mnemonic00x020L2D_CACHE_ALLOCATE |