| Field Name | Bits | Type | Reset Value | Description |
|---|
| UEN | 19 | roRead-only | 0x0 | User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RES0. |
| WT | 18 | roRead-only | 0x0 | This feature is not supported, so this bit is RES0. |
| NA | 17 | roRead-only | 0x0 | This feature is not supported, so this bit is RES0. |
| EX | 16 | roRead-only | 0x1 | Export supported. Value is IMPLEMENTATION DEFINED. |
| CCD | 15 | roRead-only | 0x1 | Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL, and RES0 otherwise. |
| CC | 14 | roRead-only | 0x1 | Dedicated cycle counter (counter 31) supported. This bit is RES1. |
| SIZE | 13:8 | roRead-only | 0x3F | Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses, and the largest counter is 64-bits, so this field is 0b111111. |
| N | 7:0 | roRead-only | 0x6 | Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31, so bits[7:5] are always RES0.and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented. |