CHKR4_CLKA_UPPER (CRL_APB) Register Description
| Register Name | CHKR4_CLKA_UPPER |
|---|---|
| Offset Address | 0x00000001A0 |
| Absolute Address | 0x00FF5E01A0 (CRL_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Upper Clock Comparison Threshold. |
CHKR4_CLKA_UPPER (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| thrshld | 31:0 | rwNormal read/write | 0x0 | Upper Threshold. This must be set up before a start bit is set (there is no clock crossing from this bus to the comparison logic.) |