CHKR4_CTRL (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CHKR4_CTRL (CRL_APB) Register Description

Register NameCHKR4_CTRL
Offset Address0x00000001AC
Absolute Address 0x00FF5E01AC (CRL_APB)
Width 9
TyperwNormal read/write
Reset Value0x00000000
DescriptionClock Checker 4 Control.

CHKR4_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
start_single 8rwNormal read/write0x0Start checking mechanism once.
0: no effect.
1: check the clock once (self clearing to 0).
The start bit must be asserted after all other control bits are set.
start_continuous 7rwNormal read/write0x0Start the checking mechanism and keep checking until bit is set back to zero.
0: single check. (or stop checking)
1: continous clock checking.
The start bit must be asserted after all other control bits are set.
Reserved 6rwNormal read/write0x0reserved
clkb_mux_ctrl 5rwNormal read/write0x00: PS_REF_CLK
1: SYSOSC_CLK
Reserved 4rwNormal read/write0x0reserved
clka_mux_ctrl 3:1rwNormal read/write0x0000: RPU clock.
001: OCM clock.
010: LPD_SWITCH_CLK clock.
011: LPD_LSBUS_CLK clock.
100: PMU clock.
101: CSU_PLL_CLK clock.
110: SYSOSC_CLK clock.
111: PS_REF_CLK clock.
Enable 0rwNormal read/write0x0This enables the checker, but does not start it.