CHKR7_CLKA_LOWER (CRL_APB) Register Description
| Register Name | CHKR7_CLKA_LOWER |
|---|---|
| Offset Address | 0x00000001D4 |
| Absolute Address | 0x00FF5E01D4 (CRL_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Lower Clock Comparison Threshold. |
CHKR7_CLKA_LOWER (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| thrshld | 31:0 | rwNormal read/write | 0x0 | Lower Threshold. This must be set up before a start bit is set (there is no clock crossing from this bus to the comparison logic.) |