CHKR7_CLKB_CNT (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CHKR7_CLKB_CNT (CRL_APB) Register Description

Register NameCHKR7_CLKB_CNT
Offset Address0x00000001D8
Absolute Address 0x00FF5E01D8 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCLK B Counting Value.

CHKR7_CLKB_CNT (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
value31:0rwNormal read/write0x0Number of cycles that the 'B' clock will count before checking if clock 'A' is within the thresholds.