CIDCVR0 (A53_ETM_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CIDCVR0 (A53_ETM_3) Register Description

Register NameCIDCVR0
Offset Address0x0000000600
Absolute Address 0x00FEF40600 (CORESIGHT_A53_ETM_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionContext ID Comparator Value Register 0

CIDCVR0 (A53_ETM_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VALUE31:0rwNormal read/write0Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by IDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset, the ETM architecture assumes that the Context ID is zero until the processor updates the Context ID.