CIDR0 (TPIU) Register Description
| Register Name | CIDR0 |
|---|---|
| Offset Address | 0x0000000FF0 |
| Absolute Address | 0x00FE980FF0 (CORESIGHT_SOC_TPIU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | A component identification register, that indicates that the identification registers are present. |
CIDR0 (TPIU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PRMBL_0 | 7:0 | roRead-only | 0x0 | Contains bits [7:0] of the component identification |