CIDR1 (A53_ETM_1) Register Description
| Register Name | CIDR1 |
|---|---|
| Offset Address | 0x0000000FF4 |
| Absolute Address | 0x00FED40FF4 (CORESIGHT_A53_ETM_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000090 |
| Description | Component Identification Register 1 |
CIDR1 (A53_ETM_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLASS | 7:4 | roRead-only | 0x9 | Component class. Reads as 0x9, to indicate that the ETM is a debug component, with CoreSight architecture compliant management registers. |
| PRMBL_1 | 3:0 | roRead-only | 0x0 | Preamble. Must read as 0x0. |