CIDR1 (ETF8K) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CIDR1 (ETF8K) Register Description

Register NameCIDR1
Offset Address0x0000000FF4
Absolute Address 0x00FE950FF4 (CORESIGHT_SOC_ETF_2)
Width32
TyperoRead-only
Reset Value0x00000090
DescriptionA component identification register, that indicates that the identification registers are present. This register also indicates the component class.

CIDR1 (ETF8K) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Class 7:4roRead-only0x9Class of the component. E.g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component identification.
Preamble 3:0roRead-only0x0Contains bits [11:8] of the component identification