CIDR1 (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CIDR1 (R5_DBG_0) Register Description

Register NameCIDR1
Offset Address0x0000000FF4
Absolute Address 0x00FEBF0FF4 (CORESIGHT_R5_DBG_0)
Width32
TyperoRead-only
Reset Value0x00000090
DescriptionComponent ID Register 1

CIDR1 (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLASS 7:4roRead-only0x9Component class: 0x9 = debug component.
PRMBL_1 3:0roRead-only0x0Preamble.