CIDR1 (TSGEN) Register Description
Register Name | CIDR1 |
---|---|
Offset Address | 0x0000000FF4 |
Absolute Address | 0x00FE900FF4 (CORESIGHT_SOC_TSGEN) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
CIDR1 (TSGEN) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CLASS | 7:4 | roRead-only | 0x0 | Class of the component, for example, ROM table or CoreSight component. |
PRMBL_1 | 3:0 | roRead-only | 0x0 | Contains bits[11:8] of the component identification code. |