CIDR2 (A53_PMU_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CIDR2 (A53_PMU_1) Register Description

Register NameCIDR2
Offset Address0x0000000FF8
Absolute Address 0x00FED30FF8 (CORESIGHT_A53_PMU_1)
Width32
TyperoRead-only
Reset Value0x00000005
DescriptionPerformance Monitors Component Identification Register 2

CIDR2 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PRMBL_2 7:0roRead-only0x5Preamble. Must read as 0x05.