CLAIMSET (A53_CTI_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CLAIMSET (A53_CTI_2) Register Description

Register NameCLAIMSET
Offset Address0x0000000FA0
Absolute Address 0x00FEE20FA0 (CORESIGHT_A53_CTI_2)
Width32
TyperwNormal read/write
Reset Value0x0000000F
DescriptionCTI Claim Set

CLAIMSET (A53_CTI_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLAIM_x31:0rwNormal read/write0xFCLAIM tag set bit. If x is greater than or equal to the IMPLEMENTATION DEFINED number of CLAIM tags, this bit is RAZ/SBZ. Software can rely on these bits reading as zero, and must use a should-be-zero policy on writes. Implementations must ignore writes.Otherwise, the bit is RAO and the behavior on writes is:A single write to CTICLAIMSET can set multiple tags to 1.