CNTCTLR1 (A53_ETM_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CNTCTLR1 (A53_ETM_3) Register Description

Register NameCNTCTLR1
Offset Address0x0000000154
Absolute Address 0x00FEF40154 (CORESIGHT_A53_ETM_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCounter Control Register 1

CNTCTLR1 (A53_ETM_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CNTCHAIN17rwNormal read/write0Controls whether counter 1 decrements when a reload event occurs for counter 0
RLDSELF16rwNormal read/write0x0Controls whether a reload event occurs for counter, when counter reaches zero:
RLDEVENT15:8rwNormal read/write0x0Selects an event, that when it occurs causes a reload event for counter.
CNTEVENT 7:0rwNormal read/write0x0Selects an event, that when it occurs causes counter to decrement.