CNTENCLR_EL0 (A53_PMU_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CNTENCLR_EL0 (A53_PMU_2) Register Description

Register NameCNTENCLR_EL0
Offset Address0x0000000C20
Absolute Address 0x00FEE30C20 (CORESIGHT_A53_PMU_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Count Enable Clear Register

CNTENCLR_EL0 (A53_PMU_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
C31rwNormal read/write0x0PMCCNTR_EL0 disable bit. Disables the cycle counter register.
P30:0rwNormal read/write0x0Event counter disable bit for EVCNTR<x>.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: