CNTENCLR_EL0 (A53_PMU_2) Register Description
Register Name | CNTENCLR_EL0 |
---|---|
Offset Address | 0x0000000C20 |
Absolute Address | 0x00FEE30C20 (CORESIGHT_A53_PMU_2) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Performance Monitors Count Enable Clear Register |
CNTENCLR_EL0 (A53_PMU_2) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
C | 31 | rwNormal read/write | 0x0 | PMCCNTR_EL0 disable bit. Disables the cycle counter register. |
P | 30:0 | rwNormal read/write | 0x0 | Event counter disable bit for EVCNTR<x>.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: |