CONFIG_1 (APU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CONFIG_1 (APU) Register Description

Register NameCONFIG_1
Offset Address0x0000000024
Absolute Address 0x00FD5C0024 (APU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionL2 Configuration

CONFIG_1 (APU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
L2RSTDISABLE29rwNormal read/write0x0Set whether to disable L2 cache invalidation at reset.
Only change this signal when the MP is in the reset state.
L1RSTDISABLE28rwNormal read/write0x0Set whether to disable L1 cache invalidation at reset.
Only change this signal when the MP is in the reset state.
CP15DISABLE 3:0rwNormal read/write0x0Set whether to disable write access to certain system registers.