CONFIG_REG0 (PLSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CONFIG_REG0 (PLSYSMON) Register Description

Register NameCONFIG_REG0
Offset Address0x0000000100
Absolute Address 0x00FFA50D00 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfiguration, Reg 0.

Mode settings for channel selection, averaging and sampling. Refer to UG1085 SysMon Chapter and UG580 for more information.

CONFIG_REG0 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15rwNormal read/write0x0reserved, set to 0.
Reserved14rwNormal read/write0x0reserved, set to 0.
averaging13:12rwNormal read/write0x0Averaging Mode enable/set. Applies to sequencer looping.
0: no averaging.
1: 16 samples.
2: 64 samples.
3: 256 samples.
external_mux11rwNormal read/write0x0Enable External Multiplexor.
0: disable.
1: enable.
Refer to channel_out[4:0] signals in PG185.
BU10rwNormal read/write0x0Select uni/bipolar Input Mode. Applies to single channel mode (not sequencing) and only external sensor channels.
0: unipolar.
1: bipolar.
A circuit diagram is shown in UG580.
EC 9rwNormal read/write0x0Enable Event-Driven Sampling Mode for ADC.
0: program driven.
1: event driven.
ACQ 8rwNormal read/write0x0Enable Long Acquisition Settling Time.
0: normal.
1: long acquisition time.
Applies to continuous sampling mode of single channel.
Reserved 7:6rwNormal read/write0x0reserved
mux_channel 5:0rwNormal read/write0x0Single-channel Mode. Select the analog sensor channel to measure using bits [5:0]. The analog channels are listed in the PL SysMon Sensor Channel table of UG1085.