CONFIG_REG0 (PSSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CONFIG_REG0 (PSSYSMON) Register Description

Register NameCONFIG_REG0
Offset Address0x0000000100
Absolute Address 0x00FFA50900 (AMS_PS_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfiguration, Reg 0.

Channel and sampling modes. Refer to SysMon Chapter and UG580 for more information. PS SysMon does not interface to external signals/mux.

CONFIG_REG0 (PSSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
averaging13:12rwNormal read/write0x0Averaging mode enable and set.
0: no averaging.
1: 16 samples.
2: 64 samples.
3: 256 samples.
Applies to sequencer looping.
EC 9rwNormal read/write0x0Reserved. Single sampling is triggered by the AMS.PS_SYSMON_CONTROL_STATUS register.
ACQ 8rwNormal read/write0x0Long Acquisition Settling Time enable.
0: normal.
1: long acquisition time.
Applies to single sampling mode of single channel.
Reserved 7:6rwNormal read/write0x0reserved
mux_channel 5:0rwNormal read/write0x0Single-channel Mode. Select the analog sensor channel to measure using bits [5:0]. The analog channels are listed in the PS SysMon and AMS Sensor Channel tables of UG1085.