CONFIG_REG1 (PLSYSMON) Register Description
| Register Name | CONFIG_REG1 |
|---|---|
| Offset Address | 0x0000000104 |
| Absolute Address | 0x00FFA50D04 (AMS_PL_SYSMON) |
| Width | 16 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Configuration, Reg 1. |
Alarm disables: 0: enabled. 1: disabled. Sequence mode, see below.
CONFIG_REG1 (PLSYSMON) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| sequence_mode | 15:12 | rwNormal read/write | 0x0 | Select Sequence Mode: 0000: Default channels; Loop sequence. 0001: Selected channels; Single pass. 0010: Selected channgls; Loop sequence (will include calibration and temperature). 0011: Single channel (sequencer off), select channel in CONFIG_REG0 [mux_channel]. 11xx: Default mode. Others: reserved |
| alarm_disable6to3 | 11:8 | rwNormal read/write | 0x0 | Alarm Disables. Bit[8] Alarm 3, VCCBRAM. Bit[9] Alarm 4, VCCPSINTLP (from PS). Bit[10] Alarm 5, VCCPSINTFP (from PS). Bit[11] Alarm 6, VCC_PSAUX (from PS). |
| Reserved | 7:4 | rwNormal read/write | 0x0 | reserved |
| alarm_disable2to0 | 3:1 | rwNormal read/write | 0x0 | Bit[2] Alarm 1, Vccint Voltage. Bit[3] Alarm 2, Vccaux Voltage. |
| over_temp_disable | 0 | rwNormal read/write | 0x0 | Alarm Disable: Over Temperature (OT). |