CONFIG_REG1 (PSSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CONFIG_REG1 (PSSYSMON) Register Description

Register NameCONFIG_REG1
Offset Address0x0000000104
Absolute Address 0x00FFA50904 (AMS_PS_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfiguration, Reg 1.

Alarm disables: 0: enabled. 1: disabled. Sequence mode, see below.

CONFIG_REG1 (PSSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
sequence_mode15:12rwNormal read/write0x0Select Sequence Mode:
0000: Default channels; Loop sequence.
0001: Selected channels; Single pass.
0010: Selected channels; Loop sequence (will include calibration and temperature).
0011: Single channel (sequencer off), select channel in CONFIG_REG0 [mux_channel].
11xx: Default mode.
Others: reserved
alarm_disable6to311:8rwNormal read/write0x0Alarm Disables.
Bit [8] Alarm 3, VCC_PSAUX.
Bit [9] Alarm 4, VCCO_PSDDR.
Bit [10] Alarm 5, VCCO_PSIO3.
Bit [11] Alarm 6,VCCO_PSIO0.
Reserved 7:4rwNormal read/write0x0reserved
alarm_disable2to0 3:1rwNormal read/write0x0Alarm Disables.
Bit [1] Alarm 0, Temp_LPD.
Bit [2] Alarm 1, VCC_PSINTLP.
Bit [3] Alarm 2, VCC_PSINTFP.
over_temp_disable 0rwNormal read/write0x0Alarm Disable: LPD Over Temperature (OT).