CONFIG_REG1 (PSSYSMON) Register Description
Register Name | CONFIG_REG1 |
---|---|
Offset Address | 0x0000000104 |
Absolute Address | 0x00FFA50904 (AMS_PS_SYSMON) |
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Configuration, Reg 1. |
Alarm disables: 0: enabled. 1: disabled. Sequence mode, see below.
CONFIG_REG1 (PSSYSMON) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
sequence_mode | 15:12 | rwNormal read/write | 0x0 | Select Sequence Mode: 0000: Default channels; Loop sequence. 0001: Selected channels; Single pass. 0010: Selected channels; Loop sequence (will include calibration and temperature). 0011: Single channel (sequencer off), select channel in CONFIG_REG0 [mux_channel]. 11xx: Default mode. Others: reserved |
alarm_disable6to3 | 11:8 | rwNormal read/write | 0x0 | Alarm Disables. Bit [8] Alarm 3, VCC_PSAUX. Bit [9] Alarm 4, VCCO_PSDDR. Bit [10] Alarm 5, VCCO_PSIO3. Bit [11] Alarm 6,VCCO_PSIO0. |
Reserved | 7:4 | rwNormal read/write | 0x0 | reserved |
alarm_disable2to0 | 3:1 | rwNormal read/write | 0x0 | Alarm Disables. Bit [1] Alarm 0, Temp_LPD. Bit [2] Alarm 1, VCC_PSINTLP. Bit [3] Alarm 2, VCC_PSINTFP. |
over_temp_disable | 0 | rwNormal read/write | 0x0 | Alarm Disable: LPD Over Temperature (OT). |