CONFIG_REG2 (PLSYSMON) Register Description
| Register Name | CONFIG_REG2 |
|---|---|
| Offset Address | 0x0000000108 |
| Absolute Address | 0x00FFA50D08 (AMS_PL_SYSMON) |
| Width | 16 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Configuration, Reg 2. |
Clock divider
CONFIG_REG2 (PLSYSMON) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| clock_divider | 15:8 | rwNormal read/write | 0x0 | ADC Clock Divide Ratio. The reference clock is divided-down to generate the ADC clock. 00h, 01h, 02h: divide by 2. 03h through FFh: divide by 3 through 255. Note: for a value of 00h, this encoding is different than the PS SysMon unit. |