CONFIG_REG2 (PSSYSMON) Register Description
| Register Name | CONFIG_REG2 |
|---|---|
| Offset Address | 0x0000000108 |
| Absolute Address | 0x00FFA50908 (AMS_PS_SYSMON) |
| Width | 16 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Configuration, Reg 2. |
Sleep mode, Clk divider.
CONFIG_REG2 (PSSYSMON) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| clock_divider | 15:8 | rwNormal read/write | 0x0 | ADC Clock Divide Ratio. The reference clock is divided-down to generate the ADC clock. 00h: divide by 8. 01h, 02h: divide by 2. 03h through FFh: divide by 3 through 255. Note: for a value of 00h, this encoding is different than the PL SysMon unit. |
| power_down | 7:4 | rwNormal read/write | 0x0 | Enable Power-down Sleep Modes. 0000: normal operation. 0001: partial sleep mode. SysOsc is operational, but all other analog circuits are in power-down. The SysOsc is left running for other units to utilize, as needed. 0010: reserved 0011: sleep mode. All analog circuits are in power-down. |