CONFIG_REG4 (PLSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CONFIG_REG4 (PLSYSMON) Register Description

Register NameCONFIG_REG4
Offset Address0x0000000110
Absolute Address 0x00FFA50D10 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionConfiguration, Reg 4.

CONFIG_REG4 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:12rwNormal read/write0x0reserved
low_rate_eos11:10rwNormal read/write0x0Configure the generation of the EOS signal relative to regular and low-rate (slow) sequencer. End of sequence to be from:
00: regular rate.
01: low-rate (slow).
10: regular and low-rate (slow).
11: regular rate (default).
sequence_rate 9:8rwNormal read/write0x0When using the low-rate sample mode, this field determines the divided down conversion rate from normal. Channels can be either a normal sample rate (SEQ_CHANNEL{0:2}) or a less frequent sample rate (SEQ_LOW_RATE_CHANNEL{0:2}).
00: every sequence.
01: every 4th Sequence.
10: every 16th Sequence
11:
every 64th Sequence.
When including a channel in the sequence, the user must ensure that each selected channel is either in the normal or low-rate sequence register, but not both. Channels not in the sequence are not selected in either sequence channel type.
Reserved 7:4rwNormal read/write0x0reserved
vuser_enable_hrange 3:0rwNormal read/write0x0Enable high range measurement (0 to 6V) on the PMBus data formater.
0: Range is 0 to 3V.
1: Range is 0 to 6V.
Bit[0] VUser0.
Bit[1] VUser1.
Bit[2] VUser2.
Bit[3] VUser3.
Note: The Vivado design suite sets this = 1 when SYSMON_VUSER[3:0]_MONITOR is either VCCO_TOP or VCCO_BOT.
For all other banks and supplies, leave = 0.