CR (APM) Register Description
Register Name | CR |
---|---|
Offset Address | 0x0000000300 |
Absolute Address |
0x00FD490300 (APM_CCI_INTC) 0x00FFA00300 (APM_INTC_OCM) 0x00FFA10300 (APM_LPD_FPD) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Control |
0: disable. 1: enable.
CR (APM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
STR_FIFO_RST | 25 | rwNormal read/write | 0x0 | 1: Resets the streaming FIFO |
GCCR_RST | 17 | rwNormal read/write | 0x0 | 1: Resets the free-running Global Clock Counter. |
GCCR_EN | 16 | rwNormal read/write | 0x0 | 1: Enables the free-running Global Clock Counter. |
LATENCY_READ_END | 7 | rwNormal read/write | 0x0 | Read Latency End Point. 1: Enables first read as read latency end point 0: Enables last read as read latency end point |
LATENCY_READ_START | 6 | rwNormal read/write | 0x0 | Read Latency Start Point. 0: Enables address issuance by the master interface as read latency start point (ARVALID)1: Enables address acceptance by slave as read latency start point (ARVALID and ARREADY) |
LATENCY_WRITE_END | 5 | rwNormal read/write | 0x0 | Write Latency End Point. 1: Enables first write as write latency end point. 0: Enables Last write as write latency end point |
LATENCY_WRITE_START | 4 | rwNormal read/write | 0x0 | Write Latency Start Point. 0: Enables address issuance by master interface as write latency start point (AWVALID). 1: Enables address acceptance by the slave interface as write latency start point (AWVALID and AWREADY) |
ID_MASKING_EN | 3 | rwNormal read/write | 0x0 | Enable ID Based Filtering/Masking. This bit is only valid in Advanced mode.0: Ignore ID for metric calculation 1: Enables ID filtering and masking. When enabled, all metric corresponds to the ID configured in the IDR and IDMR registers. |
MET_CNT_RST | 1 | rwNormal read/write | 0x0 | 1: Resets all metric counters and sampled metric counters in the monitor |
MET_CNT_EN | 0 | rwNormal read/write | 0x0 | 1: Enables all metric counters in the monitor |