CR (APM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CR (APM) Register Description

Register NameCR
Offset Address0x0000000300
Absolute Address 0x00FD490300 (APM_CCI_INTC)
0x00FFA00300 (APM_INTC_OCM)
0x00FFA10300 (APM_LPD_FPD)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionControl

0: disable. 1: enable.

CR (APM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
STR_FIFO_RST25rwNormal read/write0x01: Resets the streaming FIFO
GCCR_RST17rwNormal read/write0x01: Resets the free-running Global Clock Counter.
GCCR_EN16rwNormal read/write0x01: Enables the free-running Global Clock Counter.
LATENCY_READ_END 7rwNormal read/write0x0Read Latency End Point. 1: Enables first read as read latency end point 0: Enables last read as read latency end point
LATENCY_READ_START 6rwNormal read/write0x0Read Latency Start Point. 0: Enables address issuance by the master interface as read latency start point (ARVALID)1: Enables address acceptance by slave as read latency start point (ARVALID and ARREADY)
LATENCY_WRITE_END 5rwNormal read/write0x0Write Latency End Point. 1: Enables first write as write latency end point. 0: Enables Last write as write latency end point
LATENCY_WRITE_START 4rwNormal read/write0x0Write Latency Start Point. 0: Enables address issuance by master interface as write latency start point (AWVALID). 1: Enables address acceptance by the slave interface as write latency start point (AWVALID and AWREADY)
ID_MASKING_EN 3rwNormal read/write0x0Enable ID Based Filtering/Masking. This bit is only valid in Advanced mode.0: Ignore ID for metric calculation 1: Enables ID filtering and masking. When enabled, all metric corresponds to the ID configured in the IDR and IDMR registers.
MET_CNT_RST 1rwNormal read/write0x01: Resets all metric counters and sampled metric counters in the monitor
MET_CNT_EN 0rwNormal read/write0x01: Enables all metric counters in the monitor