CR (R5_ETM_0) Register Description
| Register Name | CR |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FEBFC000 (CORESIGHT_R5_ETM_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000421 |
| Description | Main Control Register |
CR (R5_ETM_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Core_select | 27:25 | rwNormal read/write | 0x0 | If an ETM is shared between multiple CPUs, selects which CPU to trace. For the maximum value permitted, see bits[14:12] of the System Configuration Register. To guarantee that the ETM is correctly synchronized to the new CPU, you must update these bits as follows: 1. Set bit[10], ETM programming, and bit[0], ETM power down, to 1. 2. Change the core select bits. 3. Clear bit[0], ETM power down, to 0. 4. Perform other programming required as normal. |
| Port_size_3 | 21 | rwNormal read/write | 0x0 | Use this bit in conjunction with bits[6:4]. |
| Data_only | 20 | rwNormal read/write | 0x0 | 0: Instruction trace enabled. 1: Instruction trace disabled. Data-only tracing is possible in this mode. |
| Filter | 19 | rwNormal read/write | 0x0 | Use this bit in conjunction with bit[1], the MonitorCPRT bit. |
| Suppress_data | 18 | rwNormal read/write | 0x0 | Use this bit with bit[7] to suppress data. |
| Port_mode_1_0 | 17:16 | rwNormal read/write | 0x0 | These bits are used, in conjunction with bit[13], to set the trace port clocking mode. ETM-R5 supports only dynamic mode, corresponding to the value b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit[11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode. |
| Context_ID_size | 15:14 | rwNormal read/write | 0x0 | The possible values of this field are: 00: No Context ID tracing. 01: Context ID bits[7:0] traced. 10: Context ID bits[15:0] traced. 11: Context ID bits[31:0] traced. Note: Only the number of bytes specified are traced even if the new value is larger than this. |
| Port_mode_2 | 13 | rwNormal read/write | 0x0 | See the description of bits[17:16]. |
| Cycle_accurate | 12 | rwNormal read/write | 0x0 | Set this bit to 1 if you want the trace to include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive. |
| Programming | 10 | rwNormal read/write | 0x1 | When set to 1, the ETM is being programmed. |
| Debug_request | 9 | rwNormal read/write | 0x0 | If you set this bit to 1, when the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the Arm processor to be forced into Debug state. |
| Branch_output | 8 | rwNormal read/write | 0x0 | Set this bit to 1 if you want the ETM to output all branch addresses, even if the branch is because of a direct branch instruction. Setting this bit to 1 enables reconstruction of the program flow without having access to the memory image of the code being executed. |
| Port_size_2_0 | 6:4 | rwNormal read/write | 0x2 | Use this field with bit[21] to specify the port size. The port size determines how many external pins are available to output the trace information on ATDATA[31:0]. ETM-R5 supports only the 32-bit port size, corresponding to a Port size[2:0] value of b0100, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit[10] of the System Configuration Register indicates if these bits are set to select an unsupported port size. |
| Data_access | 3:2 | rwNormal read/write | 0x0 | This field configures the data tracing mode. The possible values are: 00: No data tracing. 01: Trace only the data portion of the access. 10: Trace only the address portion of the access. 11: Trace both the address and the data of the access. |
| MonitorCPRT | 1 | rwNormal read/write | 0x0 | This field controls whether CPRTs are traced. This bit is used with bit[19]. 0: CPRTs not traced. 1: CPRTs traced. |
| Power_down | 0 | rwNormal read/write | 0x1 | A pin controlled by this bit enables the ETM power to be controlled externally. The sense of this bit is inverted, and drives the ETMPWRUP signal. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, ETM tracing is disabled and accesses to any registers other than this register and the Lock Access Register are ignored. |