CRCPARCTL0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CRCPARCTL0 (DDRC) Register Description

Register NameCRCPARCTL0
Offset Address0x00000000C0
Absolute Address 0x00FD0700C0 (DDRC)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00008000
DescriptionCRC Parity Control Register0

All register fields are dynamic, unless described otherwise in the register field description. Dynamic registers can be written at any time during operation.

CRCPARCTL0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
retry_ctrlupd_enable15rwNormal read/write0x1dfi_ctrlupd_req enable for retry.
- 1: Enable to issue dfi_ctrlupd_req before starting retry sequence
- 0: Disable to issue dfi_ctrlupd_req before starting retry sequence
The DFI controller update can be used to reset PHY FIFO pointers.
If both CRCPARCTL0.retry_cfrlupd_enable and CRCPARCTL1.alert_wait_for_sw are enabled, dfi_ctrlupd_req is issued just before software intervention time.
If CRCPARCTL0.retry_cfrlupd_enable is enabled, dfi_ctrlupd_req will be issued regardless of DFIUPD0.dis_auto_ctrlupd.
Programming Mode: Static
dfi_alert_err_max_reached_int_clr 8wtcReadable, write a 1 to clear0x0Interrupt clear bit for DFI alert counter saturation. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_max_reached_int is cleared. When the clear operation is complete, the DDRC automatically clears this bit.
dfi_alert_err_fatl_int_clr 4wtcReadable, write a 1 to clear0x0Interrupt clear bit for dfi_alert_err_fatl_int. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_fatl_int is cleared. When the clear operation is complete, the DDRC automatically clears this bit.
dfi_alert_err_cnt_clr 2wtcReadable, write a 1 to clear0x0DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRC automatically clears this bit.
dfi_alert_err_int_clr 1wtcReadable, write a 1 to clear0x0Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the DDRC automatically clears this bit.
dfi_alert_err_int_en 0rwNormal read/write0x0Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int.