CRCPARCTL0 (DDRC) Register Description
Register Name | CRCPARCTL0 |
---|---|
Offset Address | 0x00000000C0 |
Absolute Address | 0x00FD0700C0 (DDRC) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00008000 |
Description | CRC Parity Control Register0 |
All register fields are dynamic, unless described otherwise in the register field description. Dynamic registers can be written at any time during operation.
CRCPARCTL0 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
retry_ctrlupd_enable | 15 | rwNormal read/write | 0x1 | dfi_ctrlupd_req enable for retry. - 1: Enable to issue dfi_ctrlupd_req before starting retry sequence - 0: Disable to issue dfi_ctrlupd_req before starting retry sequence The DFI controller update can be used to reset PHY FIFO pointers. If both CRCPARCTL0.retry_cfrlupd_enable and CRCPARCTL1.alert_wait_for_sw are enabled, dfi_ctrlupd_req is issued just before software intervention time. If CRCPARCTL0.retry_cfrlupd_enable is enabled, dfi_ctrlupd_req will be issued regardless of DFIUPD0.dis_auto_ctrlupd. Programming Mode: Static |
dfi_alert_err_max_reached_int_clr | 8 | wtcReadable, write a 1 to clear | 0x0 | Interrupt clear bit for DFI alert counter saturation. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_max_reached_int is cleared. When the clear operation is complete, the DDRC automatically clears this bit. |
dfi_alert_err_fatl_int_clr | 4 | wtcReadable, write a 1 to clear | 0x0 | Interrupt clear bit for dfi_alert_err_fatl_int. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_fatl_int is cleared. When the clear operation is complete, the DDRC automatically clears this bit. |
dfi_alert_err_cnt_clr | 2 | wtcReadable, write a 1 to clear | 0x0 | DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRC automatically clears this bit. |
dfi_alert_err_int_clr | 1 | wtcReadable, write a 1 to clear | 0x0 | Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the DDRC automatically clears this bit. |
dfi_alert_err_int_en | 0 | rwNormal read/write | 0x0 | Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. |