CRCPARCTL1 (DDRC) Register Description
| Register Name | CRCPARCTL1 |
|---|---|
| Offset Address | 0x00000000C4 |
| Absolute Address | 0x00FD0700C4 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x10000200 |
| Description | CRC Parity Control Register1 |
This register is static. Static registers can only be written when the controller is in reset.
CRCPARCTL1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_t_phy_rdlat | 29:24 | rwNormal read/write | 0x10 | The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. This value is only used for detecting read data timeout when DDR4 retry is enabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: - 1:2 Frequency mode && DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 Unit: DFI Clocks |
| alert_wait_for_sw | 9 | rwNormal read/write | 0x1 | After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DRAM before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (CRCPARCTRL1.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesnt clear the interrupt register after handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of Parity/CRC error, there are two possibilities when the software doesnt reset MR5[4] to 0. - (i) If Persistent parity mode register bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in the Parity error log register MPR Page 1 is valid. - (ii) If Persistent parity mode register bit is SET: Parity checking is done for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in MPR Page 1 should be treated as Dont care. |
| crc_parity_retry_enable | 8 | rwNormal read/write | 0x0 | - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity or CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) |
| crc_inc_dm | 7 | rwNormal read/write | 0x0 | CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal |
| crc_enable | 4 | rwNormal read/write | 0x0 | CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. |
| parity_enable | 0 | rwNormal read/write | 0x0 | C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of C/A parity and disable detection of C/A parity error If RCDs parity error detection or SDRAMs parity detection is enabled, this register should be 1. |