CRCPARCTL2 (DDRC) Register Description
| Register Name | CRCPARCTL2 |
|---|---|
| Offset Address | 0x00000000C8 |
| Absolute Address | 0x00FD0700C8 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0030050C |
| Description | CRC Parity Control Register2 |
This register is static. Static registers can only be written when the controller is in reset.
CRCPARCTL2 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_par_alert_pw_max | 24:16 | rwNormal read/write | 0x30 | Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.MAX Program this to tPAR_ALERT_PW.MAX/2 and round up to next integer value. Values of 0, 1, and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. |
| t_crc_alert_pw_max | 12:8 | rwNormal read/write | 0x5 | Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX Program this to tCRC_ALERT_PW.MAX/2 and round up to next integer value. Values of 0, 1, and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. |
| retry_fifo_max_hold_timer_x4 | 5:0 | rwNormal read/write | 0xC | Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO before it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this register as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cycles. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC error occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recommended(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The Recommended values are minimum value to be set. For mode detail, See Calculation of FIFO Depth section. Max value can be set to this register is defined below: Full bus Mode (CRC=OFF) Max value = 39 Full bus Mode (CRC=ON) Max value = 38 Half bus Mode (CRC=OFF) Max value = 38 Half bus Mode (CRC=ON) Max value = 37 Quarter bus Mode (CRC=OFF) Max value = 36 Quarter bus Mode (CRC=ON) Max value = 34 Values of 0, 1 and 2 are illegal. |