CRF_APB Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

CRF_APB Module Description

Module Name	CRF_APB Module
Modules of this Type	CRF_APB
Base Addresses	0x00FD1A0000 (CRF_APB)
Description	FPD Clock and Reset control

CRF_APB Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
ERR_CTRL	0x0000000000	1	rwNormal read/write	0x00000000	SLVERR Error Signal Enable.
IR_STATUS	0x0000000004	1	wtcReadable, write a 1 to clear	0x00000000	APB Register Address Decode Error Interrupt Status and Clear.
IR_MASK	0x0000000008	1	roRead-only	0x00000001	Interrupt Mask.
IR_ENABLE	0x000000000C	1	woWrite-only	0x00000000	Interrupt Mask.
IR_DISABLE	0x0000000010	1	woWrite-only	0x00000000	Interrupt Disable.
CRF_WPROT	0x000000001C	1	rwNormal read/write	0x00000000	CRF_APB SLCR Write Protection.
APLL_CTRL	0x0000000020	32	rwNormal read/write	0x00012C09	APLL Clock Unit Control
APLL_CFG	0x0000000024	32	rwNormal read/write	0x00000000	APLL Integer Helper Data Configuration.
APLL_FRAC_CFG	0x0000000028	32	rwNormal read/write	0x00000000	Fractional control for the PLL
DPLL_CTRL	0x000000002C	32	rwNormal read/write	0x00002C09	DPLL Clock Unit Control
DPLL_CFG	0x0000000030	32	rwNormal read/write	0x00000000	DPLL Integer Helper Data Configuration.
DPLL_FRAC_CFG	0x0000000034	32	rwNormal read/write	0x00000000	Fractional control for the PLL
VPLL_CTRL	0x0000000038	32	rwNormal read/write	0x00012809	VPLL Clock Unit Control.
VPLL_CFG	0x000000003C	32	rwNormal read/write	0x00000000	VPLL Integer Helper Data Configuration.
VPLL_FRAC_CFG	0x0000000040	32	rwNormal read/write	0x00000000	Fractional control for the PLL.
PLL_STATUS	0x0000000044	8	roRead-only	0x00000038	FPD PLL Clocking Status.
APLL_TO_LPD_CTRL	0x0000000048	16	rwNormal read/write	0x00000400	APLL to LPD Clock Divisor.
DPLL_TO_LPD_CTRL	0x000000004C	16	rwNormal read/write	0x00000400	DPLL to LPD Clock Divisor.
VPLL_TO_LPD_CTRL	0x0000000050	16	rwNormal read/write	0x00000400	VPLL to LPD Clock Divisor.
ACPU_CTRL	0x0000000060	32	rwNormal read/write	0x03000400	APU MPCore Clock Generator Control.
DBG_TRACE_CTRL	0x0000000064	32	rwNormal read/write	0x00002500	Debug Trace Clock Generator Control.
DBG_FPD_CTRL	0x0000000068	32	rwNormal read/write	0x01002500	Debug in FPD Clock Generator Control.
DP_VIDEO_REF_CTRL	0x0000000070	32	rwNormal read/write	0x00000002	DisplayPort Video Clock Generator Control.
DP_AUDIO_REF_CTRL	0x0000000074	32	rwNormal read/write	0x01032300	DisplayPort Audio Clock Generator Control.
DP_STC_REF_CTRL	0x000000007C	32	rwNormal read/write	0x01203200	DisplayPort System Time Clock Generator Control.
DDR_CTRL	0x0000000080	32	rwNormal read/write	0x00000500	DDR Memory Controller Clock Generator Control.
GPU_REF_CTRL	0x0000000084	32	rwNormal read/write	0x00001500	GPU Clock Generator Control.
SATA_REF_CTRL	0x00000000A0	32	rwNormal read/write	0x01001600	SATA Clock Generator Control.
PCIE_REF_CTRL	0x00000000B4	32	rwNormal read/write	0x00001500	PCIe Clock Generator Control.
FPD_DMA_REF_CTRL	0x00000000B8	32	rwNormal read/write	0x01000500	FPD DMA Clock Generator Control.
DPDMA_REF_CTRL	0x00000000BC	32	rwNormal read/write	0x01000500	DisplayPort DMA Clock Generator Control.
TOPSW_MAIN_CTRL	0x00000000C0	32	rwNormal read/write	0x01000400	AXI Interconnect Clock Generator Config (TOPSW_MAIN_CLK)
TOPSW_LSBUS_CTRL	0x00000000C4	32	rwNormal read/write	0x01000800	APB Clock Generator Config (TOP_LSBUS_CLK)
DBG_TSTMP_CTRL	0x00000000F8	32	rwNormal read/write	0x00000A00	Debug Time Stamp Clock Generator Control in FPD.
RST_FPD_TOP	0x0000000100	24	rwNormal read/write	0x000F9FFE	Software Controlled FPD Resets.
RST_FPD_APU	0x0000000104	24	rwNormal read/write	0x00003D0F	Software Controlled APU MPCore Resets.
RST_DDR_SS	0x0000000108	8	rwNormal read/write	0x00000004	Software Controlled DDR Memory Controller Resets.