CRL_APB Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

CRL_APB Module Description

Module Name	CRL_APB Module
Modules of this Type	CRL_APB
Base Addresses	0x00FF5E0000 (CRL_APB)
Description	FPD Clock and Reset control

CRL_APB Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
ERR_CTRL	0x0000000000	1	rwNormal read/write	0x00000000	SLVERR Error Signal Enable.
IR_STATUS	0x0000000004	1	wtcReadable, write a 1 to clear	0x00000000	Interrupt Status and Clear.
IR_MASK	0x0000000008	1	roRead-only	0x00000001	Interrupt Mask.
IR_ENABLE	0x000000000C	1	woWrite-only	0x00000000	Interrupt Enable.
IR_DISABLE	0x0000000010	1	woWrite-only	0x00000000	Interrupt Disable.
CRL_WPROT	0x000000001C	1	rwNormal read/write	0x00000000	CRL SLCR Write Register Protection Control.
IOPLL_CTRL	0x0000000020	32	rwNormal read/write	0x00012C09	IOPLL Clock Unit Control.
IOPLL_CFG	0x0000000024	32	rwNormal read/write	0x00000000	IOPLL Integer Helper Data Config.
IOPLL_FRAC_CFG	0x0000000028	32	rwNormal read/write	0x00000000	Fractional control for the PLL
RPLL_CTRL	0x0000000030	32	rwNormal read/write	0x00012C09	RPLL Clock Unit Control.
RPLL_CFG	0x0000000034	32	rwNormal read/write	0x00000000	RPLL Integer Helper Data Configuration.
RPLL_FRAC_CFG	0x0000000038	32	rwNormal read/write	0x00000000	Fractional control for the PLL
PLL_STATUS	0x0000000040	32	mixedMixed types. See bit-field details.	0x00000018	LPD PLL Clocking Status.
IOPLL_TO_FPD_CTRL	0x0000000044	16	rwNormal read/write	0x00000400	IOPLL clock divider for distribution in FPD.
RPLL_TO_FPD_CTRL	0x0000000048	16	rwNormal read/write	0x00000400	RPLL clock divider for distribution in FPD.
USB3_DUAL_REF_CTRL	0x000000004C	32	rwNormal read/write	0x00052000	USB 3.0 Unit Clock Generator Control.
GEM0_REF_CTRL	0x0000000050	32	rwNormal read/write	0x00002500	GEM 0 Clock Generator Control.
GEM1_REF_CTRL	0x0000000054	32	rwNormal read/write	0x00002500	GEM 1 Clock Generator Control.
GEM2_REF_CTRL	0x0000000058	32	rwNormal read/write	0x00002500	GEM 2 Clock Generator Config
GEM3_REF_CTRL	0x000000005C	32	rwNormal read/write	0x00002500	GEM 3 Clock Generator Config
USB0_BUS_REF_CTRL	0x0000000060	32	rwNormal read/write	0x00052000	USB 0 Clock Generator Config
USB1_BUS_REF_CTRL	0x0000000064	32	rwNormal read/write	0x00052000	USB 1 Clock Generator Config
QSPI_REF_CTRL	0x0000000068	32	rwNormal read/write	0x01000800	Quad-SPI Clock Generator Config
SDIO0_REF_CTRL	0x000000006C	32	rwNormal read/write	0x01000F00	SDIO 0 Clock Generator Config
SDIO1_REF_CTRL	0x0000000070	32	rwNormal read/write	0x01000F00	SDIO 1 Clock Generator Config
UART0_REF_CTRL	0x0000000074	32	rwNormal read/write	0x01001800	UART 0 Clock Generator Config
UART1_REF_CTRL	0x0000000078	32	rwNormal read/write	0x01001800	UART 1 Clock Generator Config
SPI0_REF_CTRL	0x000000007C	32	rwNormal read/write	0x01001800	SPI 0 Clock Generator Config
SPI1_REF_CTRL	0x0000000080	32	rwNormal read/write	0x01001800	SPI 1 Clock Generator Config
CAN0_REF_CTRL	0x0000000084	32	rwNormal read/write	0x01001800	CAN 0 Clock Generator Config
CAN1_REF_CTRL	0x0000000088	32	rwNormal read/write	0x01001800	CAN 1 Clock Generator Config
CPU_R5_CTRL	0x0000000090	32	rwNormal read/write	0x03000600	RPU MPCore and OCM Clock Generator Config
IOU_SWITCH_CTRL	0x000000009C	32	rwNormal read/write	0x00001500	AXI Interface Clock Generator Config for LPD In/Outbound Switches
CSU_PLL_CTRL	0x00000000A0	32	rwNormal read/write	0x01001500	CSU Clock Generator Config
PCAP_CTRL	0x00000000A4	32	rwNormal read/write	0x00001500	PCAP Clock Generator Config
LPD_SWITCH_CTRL	0x00000000A8	32	rwNormal read/write	0x01000500	AXI Interface Clock Generator Config for LPD Main Switch
LPD_LSBUS_CTRL	0x00000000AC	32	rwNormal read/write	0x01001800	APB Interface Clock Generator Config for LPD IOP In/Outbound Switches
DBG_LPD_CTRL	0x00000000B0	32	rwNormal read/write	0x01002000	Debug Clock Generator Config in LPD
NAND_REF_CTRL	0x00000000B4	32	rwNormal read/write	0x00052000	NAND Clock Generator Config.
LPD_DMA_REF_CTRL	0x00000000B8	32	rwNormal read/write	0x00002000	LPD DMA Clock Generator Config.
PL0_REF_CTRL	0x00000000C0	32	rwNormal read/write	0x00052000	PL 0 Clock Generator Config.
PL1_REF_CTRL	0x00000000C4	32	rwNormal read/write	0x00052000	PL 1 Clock Generator Config.
PL2_REF_CTRL	0x00000000C8	32	rwNormal read/write	0x00052000	PL 2 Clock Generator Config.
PL3_REF_CTRL	0x00000000CC	32	rwNormal read/write	0x00052000	PL 3 Clock Generator Config.
PL0_THR_CTRL	0x00000000D0	32	mixedMixed types. See bit-field details.	0x00000001	PL Clock 0 Threshold Control and status
PL0_THR_CNT	0x00000000D4	16	rwNormal read/write	0x00000000	PL Clock 0 Count Value.
PL1_THR_CTRL	0x00000000D8	32	mixedMixed types. See bit-field details.	0x00000001	PL Clock 1 Threshold Control and status
PL1_THR_CNT	0x00000000DC	16	rwNormal read/write	0x00000000	PL Clock 1 Threshold Count Value.
PL2_THR_CTRL	0x00000000E0	32	mixedMixed types. See bit-field details.	0x00000001	PL Clock 2 Threshold Control and status
PL2_THR_CNT	0x00000000E4	16	rwNormal read/write	0x00000000	PL Clock 2 Threshold Count Value.
PL3_THR_CTRL	0x00000000E8	32	mixedMixed types. See bit-field details.	0x00000001	PL Clock 3 Threshold Control and status
PL3_THR_CNT	0x00000000FC	16	rwNormal read/write	0x00000000	PL Clock 3 Threshold Count Value.
GEM_TSU_REF_CTRL	0x0000000100	32	rwNormal read/write	0x00051000	GEM TimeStamp Clock Generator Control.
DLL_REF_CTRL	0x0000000104	8	rwNormal read/write	0x00000000	Clock Generator Control.
PSSYSMON_REF_CTRL	0x0000000108	32	rwNormal read/write	0x01001800	PS SYSMON Clock Generator Control.
I2C0_REF_CTRL	0x0000000120	32	rwNormal read/write	0x01000500	I2C 0 Clock Generator Control.
I2C1_REF_CTRL	0x0000000124	32	rwNormal read/write	0x01000500	I2C 1 Clock Generator Control.
TIMESTAMP_REF_CTRL	0x0000000128	32	rwNormal read/write	0x00001800	Timestamp Clock Generator Control.
SAFETY_CHK	0x0000000130	32	rwNormal read/write	0x00000000	Safety Endpoint Connectivity Check.
CLKMON_STATUS	0x0000000140	16	wtcReadable, write a 1 to clear	0x00000000	Clock Monitor Interrupt Status.
CLKMON_MASK	0x0000000144	16	roRead-only	0x0000FFFF	Clock Monitor Interrupt Mask.
CLKMON_ENABLE	0x0000000148	16	woWrite-only	0x00000000	Clock Monitor Interrupt Enable.
CLKMON_DISABLE	0x000000014C	16	woWrite-only	0x00000000	Clock Monitor Interrupt Disable.
CLKMON_TRIGGER	0x0000000150	16	woWrite-only	0x00000000	Clock Monitor Interrupt Trigger.
CHKR0_CLKA_UPPER	0x0000000160	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR0_CLKA_LOWER	0x0000000164	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR0_CLKB_CNT	0x0000000168	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR0_CTRL	0x000000016C	9	rwNormal read/write	0x00000000	Clock Checker 0 Control.
CHKR1_CLKA_UPPER	0x0000000170	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR1_CLKA_LOWER	0x0000000174	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR1_CLKB_CNT	0x0000000178	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR1_CTRL	0x000000017C	9	rwNormal read/write	0x00000000	Clock Checker 1 Control.
CHKR2_CLKA_UPPER	0x0000000180	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR2_CLKA_LOWER	0x0000000184	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR2_CLKB_CNT	0x0000000188	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR2_CTRL	0x000000018C	9	rwNormal read/write	0x00000000	Clock Checker 2 Control.
CHKR3_CLKA_UPPER	0x0000000190	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR3_CLKA_LOWER	0x0000000194	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR3_CLKB_CNT	0x0000000198	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR3_CTRL	0x000000019C	9	rwNormal read/write	0x00000000	Clock Checker 3 Control.
CHKR4_CLKA_UPPER	0x00000001A0	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR4_CLKA_LOWER	0x00000001A4	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR4_CLKB_CNT	0x00000001A8	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR4_CTRL	0x00000001AC	9	rwNormal read/write	0x00000000	Clock Checker 4 Control.
CHKR5_CLKA_UPPER	0x00000001B0	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR5_CLKA_LOWER	0x00000001B4	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR5_CLKB_CNT	0x00000001B8	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR5_CTRL	0x00000001BC	9	rwNormal read/write	0x00000000	Clock Checker 5 Control.
CHKR6_CLKA_UPPER	0x00000001C0	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR6_CLKA_LOWER	0x00000001C4	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR6_CLKB_CNT	0x00000001C8	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR6_CTRL	0x00000001CC	9	rwNormal read/write	0x00000000	Clock Checker 6 H723Control.
CHKR7_CLKA_UPPER	0x00000001D0	32	rwNormal read/write	0x00000000	Upper Clock Comparison Threshold.
CHKR7_CLKA_LOWER	0x00000001D4	32	rwNormal read/write	0x00000000	Lower Clock Comparison Threshold.
CHKR7_CLKB_CNT	0x00000001D8	32	rwNormal read/write	0x00000000	CLK B Counting Value.
CHKR7_CTRL	0x00000001DC	9	rwNormal read/write	0x00000000	Clock Checker 7 Control.
BOOT_MODE_USER	0x0000000200	20	mixedMixed types. See bit-field details.	0x00000000	Software controlled BOOT MODE.
BOOT_MODE_POR	0x0000000204	16	mixedMixed types. See bit-field details.	0x00000000	Hardware controlled BOOT MODE register.
RESET_CTRL	0x0000000218	8	rwNormal read/write	0x00000001	PS_SRST_B Pin Control and Trigger.
BLOCKONLY_RST	0x000000021C	4	wtcReadable, write a 1 to clear	0x00000000	Records the Reason for the Block-only Reset.
RESET_REASON	0x0000000220	16	mixedMixed types. See bit-field details.	0x00000001	Records the Reason for the Reset.
RST_LPD_IOU0	0x0000000230	16	rwNormal read/write	0x0000000F	Software Reset of Ethernet GEM Controllers
RST_LPD_IOU2	0x0000000238	32	rwNormal read/write	0x0017FFFF	IOP Software Reset Controls
RST_LPD_TOP	0x000000023C	24	rwNormal read/write	0x00188FDF	Software Reset Control for LPD System Elements.
RST_LPD_DBG	0x0000000240	16	rwNormal read/write	0x00000033	Debug control for both the LPD and FPD.
BOOT_PIN_CTRL	0x0000000250	16	mixedMixed types. See bit-field details.	0x00000000	Used to control the mode pins after boot.
BANK3_CTRL0	0x0000000270	10	rwNormal read/write	0x000003FF	Drive strength control 0 for DIO bank 3
BANK3_CTRL1	0x0000000274	10	rwNormal read/write	0x000003FF	Drive strength control 1 for DIO bank 3
BANK3_CTRL2	0x0000000278	10	rwNormal read/write	0x000003FF	Schmitt/CMOS input select for DIO bank 3
BANK3_CTRL3	0x000000027C	10	rwNormal read/write	0x000003FF	Pull-up/down select for DIO bank 3
BANK3_CTRL4	0x0000000280	10	rwNormal read/write	0x000003FF	Pull-up/down enable for DIO bank 3
BANK3_CTRL5	0x0000000284	10	rwNormal read/write	0x00000000	Slew rate control for DIO bank 3
BANK3_STATUS	0x0000000288	10	roRead-only	0x00000000	Voltage mode status for DIO bank 3