Field Name | Bits | Type | Reset Value | Description |
LC | 6 | rwNormal read/write | 0x0 | Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31].Arm deprecates use of PMCR_EL0.LC = 0. |
DP | 5 | rwNormal read/write | 0x0 | Disable cycle counter when event counting is prohibited. |
X | 4 | rwNormal read/write | 0x0 | Enable export of events in an IMPLEMENTATION DEFINED event stream. |
D | 3 | rwNormal read/write | 0x0 | Clock divider. |
C | 2 | rwNormal read/write | 0x0 | Cycle counter reset. This bit is WO. The effects of writing to this bit are:This bit is always RAZ.Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0. |
P | 1 | rwNormal read/write | 0x0 | Event counter reset. This bit is WO. The effects of writing to this bit are:This bit is always RAZ.Resetting the event counters does not clear any overflow bits to 0. |
E | 0 | rwNormal read/write | 0x0 | Enable. |