CR_EL0 (A53_PMU_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CR_EL0 (A53_PMU_3) Register Description

Register NameCR_EL0
Offset Address0x0000000E04
Absolute Address 0x00FEF30E04 (CORESIGHT_A53_PMU_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Control Register

CR_EL0 (A53_PMU_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LC 6rwNormal read/write0x0Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31].Arm deprecates use of PMCR_EL0.LC = 0.
DP 5rwNormal read/write0x0Disable cycle counter when event counting is prohibited.
X 4rwNormal read/write0x0Enable export of events in an IMPLEMENTATION DEFINED event stream.
D 3rwNormal read/write0x0Clock divider.
C 2rwNormal read/write0x0Cycle counter reset. This bit is WO. The effects of writing to this bit are:This bit is always RAZ.Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0.
P 1rwNormal read/write0x0Event counter reset. This bit is WO. The effects of writing to this bit are:This bit is always RAZ.Resetting the event counters does not clear any overflow bits to 0.
E 0rwNormal read/write0x0Enable.