CSUDMA_DST_ADDR (CSUDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CSUDMA_DST_ADDR (CSUDMA) Register Description

Register NameCSUDMA_DST_ADDR
Offset Address0x0000000800
Absolute Address 0x00FFC80800 (CSUDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDestination mem address (lsbs) for DMA stream->memory data transfer

CSUDMA_DST_ADDR (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ADDR31:2rwNormal read/write0x0Destination memory address (lsbs) for DMA stream to memory data transfer
Address is word aligned, so this field is only 30-bits. (2 lsbs are 0)
This field must be written initially before a DMA operation is started.
In this case, it indicates the memory destination address (lsbs) the DMA will begin writing to.
After the DMA has started, this field will dynamically change under DMA control to reflect the current memory destination address that is being processed by the DMA. When a BRESP is returned from memory, the ADDR will increment
by 1 word.
The readback is only valid if Burst Type is INCR (not WRAP)
The full 48-bit destination address is comprised of this field concatenated with the CSUDMA_DST_ADDR_MSB field as follows:
48-bit DST address = {CSUDMA_DST_ADDR_MSB, ADDR, 2b00}
Reserved 1:0razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.