CSUDMA_DST_CTRL (CSUDMA) Register Description
| Register Name | CSUDMA_DST_CTRL |
|---|---|
| Offset Address | 0x000000080C |
| Absolute Address | 0x00FFC8080C (CSUDMA) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x803FFA00 |
| Description | General DST DMA Control |
CSUDMA_DST_CTRL (CSUDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SSS_FIFOTHRESH | 31:25 | rwNormal read/write | 0x40 | When the DST FIFO level is greater than or equal to this programmed value, the SSS interface signal, "data_out_fifo_level_hit" will be asserted. This mechanism can be used by the SSS to flow control data that is being looped back from the SRC DMA. 7h00: Reserved etc 7h0F: Reserved 7h10: Threshold is 17 entries etc 7h7A: Threshold is 123 entries 7h7B: Reserved etc 7h7F: Reserved Note that "7h10" is the minimum and "7h7A" is the max value that should be programmed |
| APB_ERR_RESP | 24 | rwNormal read/write | 0x0 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 1b0 1: pslverr = 1b1 There is also a maskable interrupt , "INVALID_APB" that could be asserted, independent of what option is selected here. |
| ENDIANNESS | 23 | rwNormal read/write | 0x0 | When cleared (0), the DST_DMA will not change the outgoing AXI byte ordering When set (1), the DST_DMA will flip the outgoing AXI byte locations before sending to the AXI interface as follows: - Byte[3] -> Byte[0] - Byte[2] -> Byte[1] - Byte[1] -> Byte[2] - Byte[0] -> Byte[3] |
| AXI_BRST_TYPE | 22 | rwNormal read/write | 0x0 | When cleared (0), the DST_DMA will issue INCR type bursts to memory When set (1), the DST_DMA will issue AXI FIXED type bursts to memory |
| TIMEOUT_VAL | 21:10 | rwNormal read/write | 0xFFE | Set the timeout value for SRC DMA. There are 2 physical timers, qualified with TIMEOUT_EN, that will compare against this value: 1. Timeout counter starts to run when data is provided to the AXI write channel (memory) interface and backpressure is observed. As soon as backpressure is removed, the timer is reset. When timer expires, it stops running. 2. Timeout counter runs whenever the DMA is active. Whenever a data beat is provided by the SSS, the timer is reset. When timer expires, it stops running. TIMEOUT_VAL field is interpreted as follows: Final timeout value = TIMEOUT_VAL * timeout_prescale_period where "timeout_prescale_period" is the period of the enable that is generated by the TIMEOUT_PRE. Examples (prescaler set to maximum of 4096 clk (~2.5ns) cycles) 12h000: Final Timeout after 1 * (4096 * 2.5ns)] => 10.244 us 12h001: Final Timeout after 2 * (4096 * 2.5ns)] => 20.48 us etc 12hFFE: Final Timeout after 4095*(4096 * 2.5ns) => 41.93.ms 12hFFF: Special function - Clears both Timers Note that if PAUSE_MEM is asserted, timeout counter #1 will be paused and if PAUSE_STRM is asserted, timeout counter #2 will be paused. Note that writing the value of 12hFFF will cause both timers to be cleared. |
| FIFO_THRESH | 9:2 | rwNormal read/write | 0x80 | DST_FIFO programmed watermark value. This is the FIFO theshold used to trigger the FIFO_THRESHOLD_HIT interrupt. 8h00: Threshold is 0 entries 8h01: Threshold is 1 entry etc 8h80: Threshold is 128 entries Note that the interrupt will be triggered when the FIFO hits this threshold, irrespective of whether it is on the way up or down. |
| PAUSE_STRM | 1 | rwNormal read/write | 0x0 | 1: Temporarily stop the transfer of data to the internal DST data FIFO from the stream interface. This in effect will lead to the emptying of the DST FIFO. 0: DMA operates as usual. If previously PAUSED, it will continue on where it left off. Note. H/W has no means to apply backpressure to the stream interface. If PAUSE_STRM is asserted, the DMA will drop the stream data. This makes PAUSE mode functionally equivalent to as if the fifo were full. The value of PAUSE_STRM may therefore be limited to debug/verification only. |
| PAUSE_MEM | 0 | rwNormal read/write | 0x0 | 1: Temporarily stop the issuing of new write commands to memory. This in effect will eventually lead to the filling of the DST FIFO. Write memory commands that are already outstanding will continue to be processed, but no new write commands will be issued to memory while PAUSE_MEM is asserted. 0: DMA operates as usual. If previously PAUSED, it will continue on where it left off. |