CSUDMA_DST_I_STS (CSUDMA) Register Description
| Register Name | CSUDMA_DST_I_STS |
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| Offset Address | 0x0000000814 |
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| Absolute Address |
0x00FFC80814 (CSUDMA)
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | DST DMA Interrupt Status Register |
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This register holds the contents of the raw, pre-masked interrupt status bit. Even if a mask bit is set, S/W could still read this sticky bit to see if any event actually occurred. This register requires a specific write=1 to clear its contents. Writes=0 are ignored.
CSUDMA_DST_I_STS (CSUDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| Reserved | 31:8 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| FIFO_OVERFLOW | 7 | wtcReadable, write a 1 to clear | 0x0 | Indicates the DST_FIFO has overflowed. No backpressure mechanism exists on the stream interface in this direction. If the FIFO is full and 1 more data beat is produced by the stream interface, this bit will be set and the data beat will be discarded. If PAUSE_STREAM is asserted and the stream interface produces a beat of data, the beat will be discarded and FIFO_OVERFLOW will be set. |
| INVALID_APB | 6 | wtcReadable, write a 1 to clear | 0x0 | Indicates that an APB (register) access has occured to an unimplemented space (there is no register at that location). |
| THRESH_HIT | 5 | wtcReadable, write a 1 to clear | 0x0 | Indicates the DST_FIFO has reached a programmed watermark value. The watermark value is set via the FIFO_THRESH field. |
| TIMEOUT_MEM | 4 | wtcReadable, write a 1 to clear | 0x0 | Indicates timeout counter#1 has expired (DST DMA sees backpressure on AXI write data interface). Refer to TIMEOUT_VAL description for exact timeout duration and conditions. |
| TIMEOUT_STRM | 3 | wtcReadable, write a 1 to clear | 0x0 | Indicates timeout counter#2 has expired (DST DMA sees delay on SSS DST interface). Refer to TIMEOUT_VAL description for exact timeout duration and conditions. |
| AXI_BRESP_ERR | 2 | wtcReadable, write a 1 to clear | 0x0 | Indicates a memory write command produced a BRESP=DECERR/SLVERR on the AXI bus |
| DONE | 1 | wtcReadable, write a 1 to clear | 0x0 | Indicates the DMA has completed a command. The last associated AXI memory write command has been issued and processed (SIZE=0), all data has been sent (DST FIFO is empty) and all outstanding BRESPs have been received. |
| Reserved | 0 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |