CSUDMA_DST_SIZE (CSUDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CSUDMA_DST_SIZE (CSUDMA) Register Description

Register NameCSUDMA_DST_SIZE
Offset Address0x0000000804
Absolute Address 0x00FFC80804 (CSUDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDMA transfer payload for DMA stream-> memory data transfer

CSUDMA_DST_SIZE (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
SIZE28:2rwNormal read/write0x0Specifies the number of 4-byte words the DMA will transfer from stream to memory
Size is word aligned, so this field is only 27-bits. (2 lsbs are 0)
The action of writing to this register starts a DMA transfer of length SIZE, moving data from the stream interface to ADDR. In this case, it indicates the total payload that the DMA will move from stream to memory.
After the DMA has started, this field will dynamically change under DMA control to reflect the remaining payload size that the DMA must still complete. Whenever a BRESP is returned from memory, the SIZE will decrement
by 1.
Reserved 1:0razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.