CSUDMA_SRC_CRC (CSUDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CSUDMA_SRC_CRC (CSUDMA) Register Description

Register NameCSUDMA_SRC_CRC
Offset Address0x0000000010
Absolute Address 0x00FFC80010 (CSUDMA)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSRC DMA Pseudo CRC

A rudimentary scheme for allowing a "cumulative check" to be preserved for an entire data payload. Software can compute this value and compare against the hardware value to determine if data integrity was preserved.

CSUDMA_SRC_CRC (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CRC31:0rwNormal read/write0x0Pseudo CRC (Chksum) value on all data read from AXI memory. Whenever a 32-bit word is read from the memory and placed into the SRC FIFO, the word is added to the contents of this register. There is no special treatment for wrapping around of the 32-bit value. The initial value is 0, but any value can be loaded, since the register is read-writeable. The operation will continue on to the following DMA command if a previous DMA commands value has not been explicitly cleared by software.