CSUDMA_SRC_CTRL2 (CSUDMA) Register Description
| Register Name | CSUDMA_SRC_CTRL2 |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FFC80024 (CSUDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0000FFF8 |
| Description | General SRC DMA Control Register 2 |
CSUDMA_SRC_CTRL2 (CSUDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| ARCACHE | 26:24 | rwNormal read/write | 0x0 | Sets the ARCACHE bits on the AXI Read channel as follows: Bit 0 - Sets the AXI ArCache[0] signal Bit 1 - Sets the AXI ArCache[2] signal Bit 2 - Sets the AXI ArCache[3] signal Note that ArCache[1] is always driven to 1 |
| ROUTE_BIT | 23 | rwNormal read/write | 0x0 | 0: Command will be routed normally 1: Command will be routed to APU's cache controller |
| TIMEOUT_EN | 22 | rwNormal read/write | 0x0 | 0: The 2 Timeout counters are disabled 1: The 2 Timeout counters are enabled |
| TIMEOUT_PRE | 15:4 | rwNormal read/write | 0xFFF | Set the prescaler value for the timeout in clk (~2.5ns) cycles (Refer to TIMEOUT_VALUE description). The TIMEOUT_PRE field is interpreted as follows: 12h000: Prescaler enables timer every cycle 12h001: Prescaler enables timer every 2 cycles etc 12hFFF: Prescaler enables timer every 4096 cycles |
| MAX_OUTS_CMDS | 3:0 | rwNormal read/write | 0x8 | Controls the maximumum number of outstanding AXI read commands issued. The field is interpreted as follows: 4h0: Up to 1 Outstanding Read command allowed 4h1: Up to 2 Outstanding Read commands allowed etc 4h8: Up to 9 Outstanding Read commands allowed 4h9 - 4hF: Invalid. Valid range is 4h0 to 4h8. |