CSUDMA_SRC_I_EN (CSUDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CSUDMA_SRC_I_EN (CSUDMA) Register Description

Register NameCSUDMA_SRC_I_EN
Offset Address0x0000000018
Absolute Address 0x00FFC80018 (CSUDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSRC DMA Interrupt Enable

Allows enabling of interrupt bits without the need for a RMW operation. Write 1 : Enable this interrupt field field (The mask bit will be cleared - 0) Write 0 : No effect Reads to this register will return 0

CSUDMA_SRC_I_EN (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:7razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
INVALID_APB 6wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
THRESH_HIT 5wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
TIMEOUT_MEM 4wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
TIMEOUT_STRM 3wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
AXI_RDERR 2wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
DONE 1wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description
MEM_DONE 0wtcReadable, write a 1 to clear0x0See SRC DMA Interrupt Sticky Register for field description