CSUDMA_SRC_I_STS (CSUDMA) Register Description
| Register Name | CSUDMA_SRC_I_STS |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address | 0x00FFC80014 (CSUDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | SRC DMA Interrupt Status Register |
This register holds the contents of the raw, pre-masked interrupt status bit. Even if a mask bit is set, S/W could still read this sticky bit to see if any event actually occurred. This register requires a specific write=1 to clear its contents. Writes=0 are ignored.
CSUDMA_SRC_I_STS (CSUDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:7 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| INVALID_APB | 6 | wtcReadable, write a 1 to clear | 0x0 | Indicates that an APB (register) access has occured to an unimplemented space (there is no register at that location). |
| THRESH_HIT | 5 | wtcReadable, write a 1 to clear | 0x0 | Indicates the SRC_FIFO has reached a programmed watermark value. The watermark value is set via the "FIFO_THRESH" field. Note that the interrupt will be triggered when the FIFO hits this threshold, irrespective of whether it is on the way up or down. |
| TIMEOUT_MEM | 4 | wtcReadable, write a 1 to clear | 0x0 | Indicates timeout counter#2 has expired (SRC DMA sees delay on memory interface). Refer to TIMEOUT_VAL description for exact timeout duration and conditions. |
| TIMEOUT_STRM | 3 | wtcReadable, write a 1 to clear | 0x0 | Indicates timeout counter#1 has expired (SRC DMA sees backpressure on stream interface). Refer to TIMEOUT_VAL description for exact timeout duration and conditions. |
| AXI_RDERR | 2 | wtcReadable, write a 1 to clear | 0x0 | Indicates a memory read command produced a RRESP=DECERR/SLVERR on the AXI bus |
| DONE | 1 | wtcReadable, write a 1 to clear | 0x0 | Indicates the DMA has completed a command. The last associated AXI memory read has been issued and processed (SIZE=0), all data asociated with the command has been returned and consumed (SRC FIFO is flushed of the data associated with the command). Note that the SRC FIFO may however, still have data in it when "SRC_DONE" is asserted. This data is associated with the NEXT DMA command, and NOT the current one. Note that If the SIZE is programmed to 0 and the DMA is started, the "DONE" interrupt field will be asserted. |
| MEM_DONE | 0 | wtcReadable, write a 1 to clear | 0x0 | Indicates the DMA has completed the current command on the AXI memory side. The last memory read command has been issued and all outstanding data beats have been written into the SRC FIFO. Note that all data has not necessarily been consumed (SRC FIFO may still be occupied). Note too, that if the SIZE is programmed to 0 and the DMA is started, MEM_DONE will be asserted. |