CSUDMA_SRC_SIZE (CSUDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CSUDMA_SRC_SIZE (CSUDMA) Register Description

Register NameCSUDMA_SRC_SIZE
Offset Address0x0000000004
Absolute Address 0x00FFC80004 (CSUDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDMA transfer payload for DMA memory-> stream data transfer

CSUDMA_SRC_SIZE (CSUDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:29razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
SIZE28:2rwNormal read/write0x0Specifies the number of 4-byte words the DMA will transfer from memory to stream
Size is word aligned, so this field is only 27-bits. (2 lsbs are 0)
The action of writing to this register starts a DMA transfer of length SIZE, moving data from ADDR to the stream interface. In this case, it indicates the total payload that the DMA will move from memory to stream.
After the DMA has started, this field will dynamically change under DMA control to reflect the remaining payload size that the DMA must still complete. Whenever a data word is written into the SRC FIFO from memory,
SIZE will decrement
by 1. Note that if SIZE is programmed to 0, and the DMA is started, the interrupts DONE and MEM_DONE will be asserted.
Reserved 1razRead as zero0x0RESERVED. Return 0 when read. Writes ignored.
LAST_WORD 0rwNormal read/write0x0When set (1), the SRC_DMA will assert the "data_inp_last" on the stream interface when the current DMA command is completed. This signal is asserted simultaneously with the "data_inp_valid" signal associated with the final 32-bit word transfer.