CSUDMA_SRC_SIZE (CSUDMA) Register Description
Register Name | CSUDMA_SRC_SIZE |
---|---|
Offset Address | 0x0000000004 |
Absolute Address | 0x00FFC80004 (CSUDMA) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | DMA transfer payload for DMA memory-> stream data transfer |
CSUDMA_SRC_SIZE (CSUDMA) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:29 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
SIZE | 28:2 | rwNormal read/write | 0x0 | Specifies the number of 4-byte words the DMA will transfer from memory to stream Size is word aligned, so this field is only 27-bits. (2 lsbs are 0) The action of writing to this register starts a DMA transfer of length SIZE, moving data from ADDR to the stream interface. In this case, it indicates the total payload that the DMA will move from memory to stream. After the DMA has started, this field will dynamically change under DMA control to reflect the remaining payload size that the DMA must still complete. Whenever a data word is written into the SRC FIFO from memory, SIZE will decrement by 1. Note that if SIZE is programmed to 0, and the DMA is started, the interrupts DONE and MEM_DONE will be asserted. |
Reserved | 1 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
LAST_WORD | 0 | rwNormal read/write | 0x0 | When set (1), the SRC_DMA will assert the "data_inp_last" on the stream interface when the current DMA command is completed. This signal is asserted simultaneously with the "data_inp_valid" signal associated with the final 32-bit word transfer. |