| Field Name | Bits | Type | Reset Value | Description |
|---|
| R_UE | 31 | roRead-only | 0x0 | Uncorrectable error from RAM ECC |
| R_VOTER_ERROR | 30 | roRead-only | 0x0 | Self-checking voter error |
| R_COMP_ERR_23 | 29 | roRead-only | 0x0 | Self-checking error for comparator between processor #2 and #3 |
| R_COMP_ERR_13 | 28 | roRead-only | 0x0 | Self-checking error for comparator between processor #1 and #3 |
| R_COMP_ERR_12 | 27 | roRead-only | 0x0 | Self-checking error for comparator between processor #1 and #2 |
| R_MISMATCH_23_A | 26 | roRead-only | 0x0 | Lockstep mismatch between processor #2 and #3 |
| R_MISMATCH_13_A | 25 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #3 |
| R_MISMATCH_12_A | 24 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #2 |
| R_FT_ST_MISMATCH | 23 | roRead-only | 0x0 | The two FT state machines have different states |
| R_CPU_ID_MISMATCH | 22 | roRead-only | 0x0 | The two FT state machines have different failing CPUs |
| Reserved | 21:20 | roRead-only | 0x0 | |
| R_SLEEP_RESET | 19 | roRead-only | 0x0 | Reset was commanded by SW in Secure Processor through SLEEP instruction |
| R_MISMATCH_23_B | 18 | roRead-only | 0x0 | Lockstep mismatch between processor #2 and #3 |
| R_MISMATCH_13_B | 17 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #3 |
| R_MISMATCH_12_B | 16 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #2 |
| N_UE | 15 | roRead-only | 0x0 | Uncorrectable error from RAM ECC |
| N_VOTER_ERROR | 14 | roRead-only | 0x0 | Self-checking voter error |
| N_COMP_ERR_23 | 13 | roRead-only | 0x0 | Self-checking error for comparator between processor #2 and #3 |
| N_COMP_ERR_13 | 12 | roRead-only | 0x0 | Self-checking error for comparator between processor #1 and #3 |
| N_COMP_ERR_12 | 11 | roRead-only | 0x0 | Self-checking error for comparator between processor #1 and #2 |
| N_MISMATCH_23_A | 10 | roRead-only | 0x0 | Lockstep mismatch between processor #2 and #3 |
| N_MISMATCH_13_A | 9 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #3 |
| N_MISMATCH_12_A | 8 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #2 |
| N_FT_ST_MISMATCH | 7 | roRead-only | 0x0 | The two FT state machines have different states |
| N_CPU_ID_MISMATCH | 6 | roRead-only | 0x0 | The two FT state machines have different failing CPUs |
| Reserved | 5:4 | roRead-only | 0x0 | |
| N_SLEEP_RESET | 3 | roRead-only | 0x0 | Reset was commanded by SW in Secure Processor through SLEEP instruction |
| N_MISMATCH_23_B | 2 | roRead-only | 0x0 | Lockstep mismatch between processor #2 and #3 |
| N_MISMATCH_13_B | 1 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #3 |
| N_MISMATCH_12_B | 0 | roRead-only | 0x0 | Lockstep mismatch between processor #1 and #2 |