CTI Module Description
| Module Name | CTI Module |
|---|---|
| Modules of this Type | CORESIGHT_R5_CTI_0, CORESIGHT_R5_CTI_1, CORESIGHT_SOC_CTI_0, CORESIGHT_SOC_CTI_1, CORESIGHT_SOC_CTI_2 |
| Base Addresses |
0x00FEBF8000 (CORESIGHT_R5_CTI_0) 0x00FEBF9000 (CORESIGHT_R5_CTI_1) 0x00FE990000 (CORESIGHT_SOC_CTI_0) 0x00FE9A0000 (CORESIGHT_SOC_CTI_1) 0x00FE9B0000 (CORESIGHT_SOC_CTI_2) |
| Description | CoreSight Cross Trigger Interface |
CTI Module Register Summary
| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| CTICONTROL | 0x0000000000 | 32 | rwNormal read/write | 0x00000000 | The CTI Control Register enables the CTI. |
| CTIINTACK | 0x0000000010 | 32 | woWrite-only | 0x00000000 | The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the ctitrigout output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated. This register is used when the ctitrigout is used as a sticky output, that is, no hardware acknowledge is supplied, and a software acknowledge is required. |
| CTIAPPSET | 0x0000000014 | 32 | woWrite-only | 0x00000000 | The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised, corresponding to the bit written to. |
| CTIAPPCLEAR | 0x0000000018 | 32 | woWrite-only | 0x00000000 | The CTI Interrupt Acknowledge Register is write-only. A write to this register causes a channel event to be cleared, corresponding to the bit written to. |
| CTIAPPPULSE | 0x000000001C | 32 | woWrite-only | 0x00000000 | The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse, one cticlk period, to be generated, corresponding to the bit written to. The pulse external to the ECT can be extended to multi-cycle by the handshaking interface circuits. This register clears itself immediately, so it can be repeatedly written to without software having to clear it. |
| CTIINEN0 | 0x0000000020 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger 0 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN1 | 0x0000000024 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger 1 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN2 | 0x0000000028 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN3 | 0x000000002C | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN4 | 0x0000000030 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN5 | 0x0000000034 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN6 | 0x0000000038 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN7 | 0x000000003C | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIOUTEN0 | 0x00000000A0 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN1 | 0x00000000A4 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 1 Enable Registers define which channels can generate a ctitrigout[1] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN2 | 0x00000000A8 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 2 Enable Registers define which channels can generate a ctitrigout[2] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN3 | 0x00000000AC | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN4 | 0x00000000B0 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 4 Enable Registers define which channels can generate a ctitrigout[4] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN5 | 0x00000000B4 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 5 Enable Registers define which channels can generate a ctitrigout[5] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN6 | 0x00000000B8 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 6 Enable Registers define which channels can generate a ctitrigout[6] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN7 | 0x00000000BC | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTITRIGINSTATUS | 0x0000000130 | 32 | roRead-only | 0x00000000 | The CTI Trigger In Status Register provides the status of the ctitrigin inputs. |
| CTITRIGOUTSTATUS | 0x0000000134 | 32 | roRead-only | 0x00000000 | The CTI Trigger Out Status Register provides the status of the ctitrigout outputs. |
| CTICHINSTATUS | 0x0000000138 | 32 | roRead-only | 0x00000000 | The CTI Channel In Status Register provides the status of the ctichin inputs. |
| CTICHOUTSTATUS | 0x000000013C | 32 | roRead-only | 0x00000000 | The CTI Channel Out Status Register provides the status of the CTI ctichout outputs. |
| CTIGATE | 0x0000000140 | 32 | rwNormal read/write | 0x0000000F | The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs. It can be used effectively with CTIAPPSET, CTIAPPCLEAR, and CTIAPPPULSE for asserting trigger outputs by asserting channels, without affecting the rest of the system. On reset, this register is 0xF, and channel propagation is enabled. |
| ASICCTL | 0x0000000144 | 32 | rwNormal read/write | 0x00000000 | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0]. |
| ITCHINACK | 0x0000000EDC | 32 | woWrite-only | 0x00000000 | This register is a write-only register. It can be used to set the value of the CTCHINACK outputs. |
| ITTRIGINACK | 0x0000000EE0 | 32 | woWrite-only | 0x00000000 | This register is a write-only register. It can be used to set the value of the CTTRIGINACK outputs. |
| ITCHOUT | 0x0000000EE4 | 32 | woWrite-only | 0x00000000 | This register is a write-only register. It can be used to set the value of the CTCHOUT outputs. |
| ITTRIGOUT | 0x0000000EE8 | 32 | woWrite-only | 0x00000000 | This register is a write-only register. It can be used to set the value of the CTTRIGOUT outputs. |
| ITCHOUTACK | 0x0000000EEC | 32 | roRead-only | 0x00000000 | This register is a read-only register. It can be used to read the values of the CTCHOUTACK inputs. |
| ITTRIGOUTACK | 0x0000000EF0 | 32 | roRead-only | 0x00000000 | This register is a read-only register. It can be used to read the values of the CTTRIGOUTACK inputs. |
| ITCHIN | 0x0000000EF4 | 32 | roRead-only | 0x00000000 | This register is a read-only register. It can be used to read the values of the CTCHIN inputs. |
| ITTRIGIN | 0x0000000EF8 | 32 | roRead-only | 0x00000000 | This register is a read-only register. It can be used to read the values of the CTTRIGIN inputs. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving. Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection. |
| CLAIMSET | 0x0000000FA0 | 32 | rwNormal read/write | 0x00000000 | This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read. |
| CLAIMCLR | 0x0000000FA4 | 32 | rwNormal read/write | 0x00000000 | This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read. |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the component. |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers, except the Lock Access Register.External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. This register reads as 0 when read from an external debugger (paddrdbg31 = 1). |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x00000000 | Reports what functionality is currently permitted by the authentication interface. |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00040800 | This register indicates the capabilities of the CTI. |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
| PIDR5 | 0x0000000FD4 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR6 | 0x0000000FD8 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR7 | 0x0000000FDC | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number. |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision. |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields. |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |