CTIINEN3 (CTI) Register Description
Register Name | CTIINEN3 |
---|---|
Offset Address | 0x000000002C |
Absolute Address |
0x00FEBF802C (CORESIGHT_R5_CTI_0) 0x00FEBF902C (CORESIGHT_R5_CTI_1) 0x00FE99002C (CORESIGHT_SOC_CTI_0) 0x00FE9A002C (CORESIGHT_SOC_CTI_1) 0x00FE9B002C (CORESIGHT_SOC_CTI_2) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
CTIINEN3 (CTI) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
TRIGINEN | 3:0 | rwNormal read/write | 0x0 | Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, it enables the ctitrigin signal to generate an event on the respective channel of the CTM. For example, TRIGINEN[0] set to 1 enables ctitrigin onto channel 0. Writing a 0 to any of the bits in this register disables the ctitrigin signal from generating an event on the respective channel of the CTM.Reading this register returns the programmed value. |