CTIINEN4 (A53_CTI_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CTIINEN4 (A53_CTI_1) Register Description

Register NameCTIINEN4
Offset Address0x0000000030
Absolute Address 0x00FED20030 (CORESIGHT_A53_CTI_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations.

CTIINEN4 (A53_CTI_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TRIGINEN 3:0rwNormal read/write0x0Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, it enables the ctitrigin signal to generate an event on the respective channel of the CTM. For example, TRIGINEN[0] set to 1 enables ctitrigin onto channel 0. Writing a 0 to any of the bits in this register disables the ctitrigin signal from generating an event on the respective channel of the CTM.Reading this register returns the programmed value.