CTIOUTEN0 (CTI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CTIOUTEN0 (CTI) Register Description

Register NameCTIOUTEN0
Offset Address0x00000000A0
Absolute Address 0x00FEBF80A0 (CORESIGHT_R5_CTI_0)
0x00FEBF90A0 (CORESIGHT_R5_CTI_1)
0x00FE9900A0 (CORESIGHT_SOC_CTI_0)
0x00FE9A00A0 (CORESIGHT_SOC_CTI_1)
0x00FE9B00A0 (CORESIGHT_SOC_CTI_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs.

CTIOUTEN0 (CTI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TRIGOUTEN 3:0rwNormal read/write0x0Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, the channel input (ctichin) from the CTM is routed to the ctitrigout output. For example, enabling bit 0 enables ctichin[0] to cause a trigger event on the ctitrigout[0] output. When a 0 is written to any of the bits in this register, the channel input (ctichin) from the CTM is not routed to the ctitrigout output.Reading this register returns the programmed value.