CTR (R5_DBG_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CTR (R5_DBG_1) Register Description

Register NameCTR
Offset Address0x0000000D04
Absolute Address 0x00FEBF2D04 (CORESIGHT_R5_DBG_1)
Width32
TyperoRead-only
Reset Value0x8003C003
DescriptionCache Type Register

CTR (R5_DBG_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28roRead-only0x8Always b1000.
CWG27:24roRead-only0x0CWG Cache Write-back Granule. 0x0= No information provided. See maximum cache line size in c0, Cache Size ID Registeron page 4-34.
ERG23:20roRead-only0x0ERG Exclusives Reservation Granule. 0x0= No information provided.
DMinLine19:16roRead-only0x3DMinLine Indicates log2 of the number of words in the smallest cache line of the data and unified caches controlled by the processor: 0x3= Eight words in an L1 data cache line.
Reserved15:14roRead-only0x3Always 0x3.
Reserved13:4roRead-only0x0Always 0x000.
IMinLine 3:0roRead-only0x3IMinLine Indicates log2 of the number of words in the smallest cache line of the instruction caches controlled by the processor: 0x3- Eight words in an L1 instruction cache line.